PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 278

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2420/2520/4420/4520
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39631A-page 276
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG =
FLAG_REG =
Q1
register ‘f’
Bit Clear f
BCF
0
0
a
0
None
Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
BCF
Read
1001
Q2
f
b
[0,1]
f<b>
255
7
f, b {,a}
C7h
47h
FLAG_REG,
bbba
Process
Data
Q3
95 (5Fh). See
ffff
7, 0
register ‘f’
Write
Q4
ffff
Preliminary
BN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If NEGATIVE =
If NEGATIVE =
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Negative
BN
-128
if NEGATIVE bit is ‘1’
(PC) + 2 + 2n
None
If the NEGATIVE bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
 2004 Microchip Technology Inc.
n
n
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
127
0110
BN
operation
Process
Process
Data
Data
PC
Q3
Q3
No
Jump
nnnn
Write to PC
operation
operation
Q4
No
Q4
No
nnnn