PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 282

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2420/2520/4420/4520
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39631A-page 280
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
Q1
Q1
Q1
No
No
No
PC
PC
Bit Test File, Skip if Clear
BTFSC f, b {,a}
0
0
a
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f
See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
FALSE
TRUE
register ‘f’
operation
operation
operation
1011
Read
f
b
=
=
=
=
=
Q2
Q2
No
Q2
No
No
[0,1]
NOP
255
7
by a 2-word instruction.
address (HERE)
0;
address (TRUE)
1;
address (FALSE)
BTFSC
:
:
is executed instead, making
bbba
operation
operation
operation
Process
Data
Q3
Q3
No
Q3
No
No
95 (5Fh).
FLAG, 1, 0
ffff
operation
operation
operation
operation
Q4
Q4
Q4
No
No
No
No
ffff
Preliminary
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
Q1
Q1
No
Q1
No
No
PC
PC
Bit Test File, Skip if Set
BTFSS f, b {,a}
0
0
a
None
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
skip if (f<b>) = 1
If bit ‘b’ in register ‘f’ is ‘1’, then the next
register ‘f’
operation
operation
operation
HERE
FALSE
TRUE
1010
f
b < 7
Read
[0,1]
Q2
Q2
No
Q2
No
No
=
=
=
=
=
NOP
 2004 Microchip Technology Inc.
255
3 cycles if skip and followed
by a 2-word instruction.
address (HERE)
0;
address (FALSE)
1;
address (TRUE)
is executed instead, making
BTFSS
:
:
bbba
operation
operation
operation
Process
Data
Q3
Q3
No
Q3
No
No
95 (5Fh).
FLAG, 1, 0
ffff
operation
operation
operation
operation
Q4
No
Q4
No
No
Q4
No
ffff