PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 216

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2420/2520/4420/4520
FIGURE 18-7:
TABLE 18-6:
18.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event con-
sists of a high-to-low transition on the RX/DT line. (This
coincides with the start of a Sync Break or a Wake-up
Signal character for the LIN protocol.)
DS39631A-page 214
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Note:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input.
causing the OERR (overrun) bit to be set.
Reserved in 28-pin devices; always maintain these bits clear.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
EUSART Receive Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL
ABDOVF
PSPIF
PSPIE
PSPIP
SPEN
CSRC
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
bit 7/8
Preliminary
Stop
INT0IE
CREN
SYNC
SCKP
bit
TXIE
TXIP
Bit 4
TXIF
Word 1
RCREG
Start
bit
ADDEN
SENDB
bit 0
BRG16
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 18-8) and asynchronously, if the device is in
Sleep mode (Figure 18-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
The RCREG (receive buffer) is read after the third word
TMR0IF
CCP1IE
CCP1IP
CCP1IF
bit 7/8
BRGH
FERR
Word 2
RCREG
Bit 2
—
Stop
bit
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
Start
 2004 Microchip Technology Inc.
WUE
Bit 1
bit
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
RBIF
bit 7/8
Bit 0
Stop
bit
on page
Values
Reset
49
52
52
52
51
51
51
51
51
51