PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 141

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.0
PIC18F2420/2520/4420/4520 devices all have two
CCP (Capture/Compare/PWM) modules. Each module
contains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
In 28-pin devices, the two standard CCP modules (CCP1
and CCP2) operate as described in this chapter. In 40/
44-pin devices, CCP1 is implemented as an enhanced
CCP module with standard Capture and Compare
modes and enhanced PWM modes. The ECCP imple-
mentation is discussed in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
REGISTER 15-1:
 2004 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULES
bit 7-6
bit 5-4
bit 3-0
CCPXCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES)
bit 7
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCP pin low; on compare match, force CCP pin high
1001 = Compare mode: initialize CCP pin high; on compare match, force CCP pin low
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set,
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
11xx = PWM mode
Legend:
R = Readable bit
-n = Value at POR
U-0
—
(CCPIF bit is set)
(CCPIF bit is set)
CCP pin reflects I/O state)
CCP2 match (CCPxIF bit is set)
U-0
—
PIC18F2420/2520/4420/4520
DCxB1
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
DCxB0
R/W-0
The Capture and Compare operations described in this
chapter apply to all standard and enhanced CCP
modules.
Note: Throughout this section and Section 16.0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to gener-
ically by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the mod-
ule control register, regardless of whether the
CCP module is a standard or enhanced
implementation.
CCPxM3
R/W-0
CCPxM2 CCPxM1 CCPxM0
R/W-0
x = Bit is unknown
R/W-0
DS39631A-page 139
R/W-0
bit 0