PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 379

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

DC Characteristics ........................................................... 335
DCFSNZ .......................................................................... 287
DECF ............................................................................... 286
DECFSZ ........................................................................... 287
Demonstration Boards
Development Support ...................................................... 317
Device Differences ........................................................... 371
Device Overview .................................................................. 7
Device Reset Timers .......................................................... 45
Direct Addressing ............................................................... 69
E
Effect on Standard PIC Instructions ................................. 314
Effects of Power Managed Modes on
Electrical Characteristics .................................................. 323
Enhanced Capture/Compare/PWM (ECCP) .................... 147
Enhanced PWM Mode. See PWM (ECCP Module).
Enhanced Universal Synchronous Asynchronous
Equations
Errata ................................................................................... 6
EUSART
 2004 Microchip Technology Inc.
Power-Down and Supply Current ............................ 326
Supply Voltage ......................................................... 325
PICDEM 1 ................................................................ 320
PICDEM 17 .............................................................. 321
PICDEM 18R ........................................................... 321
PICDEM 2 Plus ........................................................ 320
PICDEM 3 ................................................................ 320
PICDEM 4 ................................................................ 320
PICDEM LIN ............................................................ 321
PICDEM USB ........................................................... 321
PICDEM.net Internet/Ethernet ................................. 320
Details on Individual Family Members ......................... 8
Features (table) ............................................................ 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Time-out Sequence .................................................... 45
Various Clock Sources ............................................... 31
Associated Registers ............................................... 160
Capture and Compare Modes .................................. 148
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 148
Pin Configurations for ECCP1 ................................. 148
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 148
Timer Resources ...................................................... 148
Receiver Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 228
A/D Minimum Charging Time ................................... 228
Asynchronous Mode ................................................ 211
Baud Rate Generator
12-Bit Break Transmit and Receive ................. 216
Associated Registers, Receive ........................ 214
Associated Registers, Transmit ....................... 212
Auto-Wake-up on Sync Break ......................... 214
Receiver ........................................................... 213
Setting up 9-Bit Mode with
Transmitter ....................................................... 211
Operation in Power Managed Mode ................ 205
Address Detect ........................................ 213
PIC18F2420/2520/4420/4520
Preliminary
Evaluation and Programming Tools ................................. 321
Extended Instruction Set
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor ........................................... 249, 261
Fast Register Stack ........................................................... 56
Firmware Instructions ...................................................... 267
Flash Program Memory ..................................................... 73
FSCM. See Fail-Safe Clock Monitor.
G
General Call Address Support ......................................... 184
GOTO .............................................................................. 288
Baud Rate Generator (BRG) ................................... 205
Synchronous Master Mode ...................................... 217
Synchronous Slave Mode ........................................ 220
ADDFSR .................................................................. 310
ADDULNK ............................................................... 310
and Using MPLAB Tools ......................................... 316
CALLW .................................................................... 311
Considerations for Use ............................................ 314
MOVSF .................................................................... 311
MOVSS .................................................................... 312
PUSHL ..................................................................... 312
SUBFSR .................................................................. 313
SUBULNK ................................................................ 313
Syntax ...................................................................... 309
Exiting Operation ..................................................... 261
Interrupts in Power Managed Modes ....................... 262
POR or Wake from Sleep ........................................ 262
WDT During Oscillator Failure ................................. 261
Associated Registers ................................................. 81
Control Registers ....................................................... 74
Erase Sequence ........................................................ 78
Erasing ...................................................................... 78
Operation During Code-Protect ................................. 81
Reading ..................................................................... 77
Table Pointer
Table Pointer Boundaries .......................................... 76
Table Reads and Table Writes .................................. 73
Write Sequence ......................................................... 79
Writing To .................................................................. 79
Associated Registers ....................................... 206
Auto-Baud Rate Detect .................................... 209
Baud Rate Error, Calculating ........................... 206
Baud Rates, Asynchronous Modes ................. 207
High Baud Rate Select (BRGH Bit) ................. 205
Sampling ......................................................... 205
Associated Registers, Receive ........................ 219
Associated Registers, Transmit ....................... 218
Reception ........................................................ 219
Transmission ................................................... 217
Associated Registers, Receive ........................ 221
Associated Registers, Transmit ....................... 220
Reception ........................................................ 221
Transmission ................................................... 220
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ........................ 76
TBLPTR (Table Pointer) Register ...................... 76
Boundaries Based on Operation ....................... 76
Protection Against Spurious Writes ................... 81
Unexpected Termination ................................... 81
Write Verify ........................................................ 81
DS39631A-page 377