PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 255

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 23-4:
REGISTER 23-5:
 2004 Microchip Technology Inc.
bit 7
bit 6-3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5-3
bit 2
bit 1
bit 0
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
bit 7
MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RE3 input pin disabled
0 = RE3 input pin enabled; MCLR disabled
Unimplemented: Read as ‘0’
LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation
PBADEN: PORTB A/D Enable bit
(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)
1 = PORTB<4:0> pins are configured as analog input channels on Reset
0 = PORTB<4:0> pins are configured as digital I/O on Reset
CCP2MX: CCP2 Mux bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
bit 7
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
Unimplemented: Read as ‘0’
LVP: Single-Supply ICSP Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Legend:
R = Readable bit
-n = Value when device is unprogrammed
Legend:
R = Readable bit
-n = Value when device is unprogrammed
MCLRE
DEBUG
R/P-1
R/P-1
XINST
R/P-0
U-0
—
PIC18F2420/2520/4420/4520
P = Programmable bit
C = Clearable bit
U-0
U-0
—
Preliminary
—
U-0
—
U-0
—
U-0
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
—
U-0
—
LPT1OSC
R/P-0
R/P-1
LVP
PBADEN
R/P-1
U-0
—
DS39631A-page 253
CCP2MX
STVREN
R/P-1
R/P-1
bit 0
bit 0