PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 127

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.3
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>)
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256 in power-of-2 increments are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
TABLE 11-1:
 2004 Microchip Technology Inc.
TMR0L
TMR0H
INTCON
T0CON
TRISA
Legend: Shaded cells are not used by Timer0.
Note 1:
Note:
Name
Prescaler
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Timer0 Register, Low Byte
Timer0 Register, High Byte
GIE/GIEH PEIE/GIEL TMR0IE
TMR0ON
RA7
Bit 7
which
REGISTERS ASSOCIATED WITH TIMER0
(1)
determine
T08BIT
RA6
Bit 6
(1)
the
T0CS
Bit 5
RA5
PIC18F2420/2520/4420/4520
prescaler
Preliminary
INT0IE
T0SE
Bit 4
RA4
11.3.1
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clear-
ing the TMR0IE bit (INTCON<5>). Before re-enabling
the interrupt, the TMR0IF bit must be cleared in
software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
RBIE
Bit 3
PSA
RA3
Timer0 Interrupt
TMR0IF
T0PS2
SWITCHING PRESCALER
ASSIGNMENT
Bit 2
RA2
INT0IF
T0PS1
Bit 1
RA1
T0PS0
RBIF
Bit 0
RA0
DS39631A-page 125
on page
Values
Reset
50
50
49
50
52