PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 284

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2420/2520/4420/4520
BZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39631A-page 282
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If ZERO
If ZERO
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Zero
BZ
-128
if ZERO bit is ‘1’
(PC) + 2 + 2n
None
If the ZERO bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
=
=
n
n
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
127
0000
BZ
operation
Process
Process
Data
Data
PC
Q3
Q3
No
Jump
nnnn
Write to PC
operation
operation
Q4
Q4
No
No
nnnn
Preliminary
CALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PC
TOS
WS
BSRS
STATUSS =
Q1
No
=
=
=
=
=
Read literal
operation
Subroutine Call
CALL k {,s}
0
s
(PC) + 4
k
if s = 1
(W)
(Status)
(BSR)
None
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, Status and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALL
2
2
HERE
‘k’<7:0>,
1110
1111
Q2
No
address (HERE)
address (THERE)
address (HERE + 4)
W
BSR
Status
k
[0,1]
PC<20:1>,
 2004 Microchip Technology Inc.
is a two-cycle instruction.
WS,
1048575
BSRS
STATUSS,
k
TOS,
110s
PUSH PC to
CALL
19
operation
kkk
stack
Q3
No
THERE, 1
k
kkkk
7
kkk
Read literal
Write to PC
‘k’<19:8>,
operation
Q4
No
kkkk
kkkk
0
8