PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 385

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

 2004 Microchip Technology Inc.
Baud Rate Generator with Clock Arbitration ............ 188
BRG Overflow Sequence ......................................... 210
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 345
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision During Start Condition
Bus Collision for Transmit and Acknowledge ........... 195
Capture/Compare/PWM (CCP) ................................ 347
CLKO and I/O .......................................................... 344
Clock Synchronization ............................................. 181
Clock/Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 349
Example SPI Master Mode (CKE = 1) ..................... 350
Example SPI Slave Mode (CKE = 0) ....................... 351
Example SPI Slave Mode (CKE = 1) ....................... 352
External Clock (All Modes except PLL) .................... 342
Fail-Safe Clock Monitor (FSCM) .............................. 262
First Start Bit Timing ................................................ 189
Full-Bridge PWM Output .......................................... 153
Half-Bridge PWM Output ......................................... 152
High/Low-Voltage Detect Characteristics ................ 339
High/Low-Voltage Detect Operation
High/Low-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4420/4520) ................... 348
Parallel Slave Port (PSP) Read ............................... 121
Parallel Slave Port (PSP) Write ............................... 121
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 155
PWM Direction Change at Near
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 353
C Bus Start/Stop Bits ............................................. 353
C Master Mode (7 or 10-Bit Transmission) ........... 192
C Master Mode (7-Bit Reception) .......................... 193
C Slave Mode (10-Bit Reception, SEN = 0) .......... 178
C Slave Mode (10-Bit Reception, SEN = 1) .......... 183
C Slave Mode (10-Bit Transmission) ..................... 179
C Slave Mode (7-bit Reception, SEN = 0) ............. 176
C Slave Mode (7-Bit Reception, SEN = 1) ............ 182
C Slave Mode (7-Bit Transmission) ....................... 177
C Slave Mode General Call Address
C Stop Condition Receive or
During Start Condition ..................................... 197
Start Condition (Case 1) .................................. 198
Start Condition (Case 2) .................................. 198
(SCL = 0) ......................................................... 197
(Case 1) ........................................................... 199
(Case 2) ........................................................... 199
(SDA only) ....................................................... 196
(VDIRMAG = 0) ................................................ 245
(VDIRMAG = 1) ................................................ 246
Sequence (7 or 10-Bit Address Mode) ............ 184
Transmit Mode ................................................. 194
Auto-Restart Disabled) .................................... 158
Auto-Restart Enabled) ..................................... 158
100% Duty Cycle ............................................. 155
2
2
C Bus Data ........................................ 355
C Bus Start/Stop Bits ........................ 355
PIC18F2420/2520/4420/4520
Preliminary
Timing Diagrams and Specifications ............................... 342
PWM Output ............................................................ 144
Repeat Start Condition ............................................ 190
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 216
Slave Synchronization ............................................. 167
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 166
SPI Mode (Slave Mode, CKE = 0) ........................... 168
SPI Mode (Slave Mode, CKE = 1) ........................... 168
Synchronous Reception
Synchronous Transmission ..................................... 217
Synchronous Transmission (Through TXEN) .......... 218
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 346
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition Timing for Entry to Idle Mode .................... 38
Transition Timing for Wake from
Transition to RC_RUN Mode ..................................... 36
USART Synchronous Receive
USART Synchronous Transmission
A/D Conversion Requirements ................................ 359
Capture/Compare/PWM Requirements ................... 347
CLKO and I/O Requirements ................................... 344
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
External Clock Requirements .................................. 342
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
2
2
C Bus Data Requirements (Slave Mode) .............. 354
C Bus Start/Stop Bits Requirements
Oscillator Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 345
V
(Master Mode, SREN) ..................................... 219
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 260
PRI_RUN Mode ................................................. 36
PRI_RUN Mode (HSPLL) .................................. 35
Idle to Run Mode ............................................... 38
(Master/Slave) ................................................. 357
(Master/Slave) ................................................. 357
(Master Mode, CKE = 0) .................................. 349
(Master Mode, CKE = 1) .................................. 350
(Slave Mode, CKE = 0) .................................... 351
(Slave Mode, CKE = 1) .................................... 352
(Slave Mode) ................................................... 353
Requirements .................................................. 355
(PIC18F4420/4520) ......................................... 348
DD
Rise > T
2
2
C Bus Data Requirements ................ 356
C Bus Start/Stop Bits
PWRT
DD
DD
) ............................................ 47
) .......................................... 47
, V
DD
DD
DD
, Case 1) ...................... 46
, Case 2) ...................... 46
Rise < T
DD
DS39631A-page 383
,
PWRT
) ........... 46