EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 105

• Manufacturer Part Number: EP2S130F1020I5N
• Manufacturer: Altera

Specifications of EP2S130F1020I5N

• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
May 2007
484-pin FineLine BGA
672-pin FineLine BGA
484-pin FineLine BGA
672-pin FineLine BGA
Table 2–21. EP2S15 Device Differential Channels
Table 2–22. EP2S30 Device Differential Channels
Package
Package
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
device, PLL 1 can drive a maximum of 10 transmitter channels in I/O
bank 1 or a maximum of 19 transmitter channels in I/O banks 1 and 2. The
Quartus II software may also merge receiver and transmitter PLLs when
a receiver is driving a transmitter. In this case, one fast PLL can drive both
the maximum numbers of receiver and transmitter channels.
Transmitter/
Transmitter/
Receiver
Receiver
Channels
Channels
38
42
42
38
42
62
38
58
Total
Total
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Note (1)
Note (1)
PLL 1
PLL 1
10
19
11
21
10
19
11
21
10
19
11
21
16
29
17
31
Stratix II Device Handbook, Volume 1
PLL 2
PLL 2
Center Fast PLLs
Center Fast PLLs
19
10
21
19
10
21
19
10
21
13
29
14
31
9
9
9
Stratix II Architecture
PLL 3
PLL 3
19
10
21
19
10
21
19
10
21
13
29
14
31
9
9
9
PLL 4
PLL 4
10
19
11
21
10
19
11
21
10
19
11
21
16
29
17
31
2–97