EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 187

EP2S130F1020I5N

Manufacturer Part Number
EP2S130F1020I5N
Description
Manufacturer
Altera
Datasheet

Specifications of EP2S130F1020I5N

Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
742
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S130F1020I5N
Manufacturer:
ALTERA
Quantity:
215
Part Number:
EP2S130F1020I5N
Manufacturer:
ALTERA
0
Part Number:
EP2S130F1020I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP2S130F1020I5N
0
Altera Corporation
April 2011
Notes to
(1)
(2)
(3)
Input delay from
pin to internal
cells
Input delay from
pin to input
register
Delay from
output register
to output pin
Output enable
pin delay
Table 5–69. Stratix II IOE Programmable Delay on Column Pins
Parameter
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Table
5–69:
Pad to I/O
dataout to logic
array
Pad to I/O input
register
I/O output
register to pad
t
Paths Affected
X Z
, t
Z X
IOE Programmable Delay
See
Tables 5–69
Available
Settings
64
8
2
2
Offset
and
Min
(ps)
Timing
Minimum
0
0
0
0
0
0
0
0
5–70
Offset
1,696
1,781
1,955
2,053
Max
(ps)
316
332
305
320
(2)
for IOE programmable delay.
Offset
(ps)
Min
Grade
-3 Speed
0
0
0
0
0
0
0
0
Note (1)
Stratix II Device Handbook, Volume 1
Offset
2,881
3,025
3,275
3,439
(3)
Max
(ps)
500
525
483
507
DC & Switching Characteristics
Offset
(ps)
Min
-4 Speed
0
0
0
0
Grade
Offset
3,313
3,766
Max
(ps)
575
556
Offset
(ps)
Min
0
0
0
0
-5 Speed
Grade
Offset
3,860
4,388
Max
(ps)
670
647
5–51

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