EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 214

EP2S130F1020I5N

Manufacturer Part Number
EP2S130F1020I5N
Description
Manufacturer
Altera
Datasheet

Specifications of EP2S130F1020I5N

Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
742
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant

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Duty Cycle Distortion
Figure 5–8. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
5–78
Stratix II Device Handbook, Volume 1
clk
INPUT
VCC
Figure 5–7. Duty Cycle Distortion
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions
present on the input clock signal or caused by the clock input buffer or
different input I/O standard does not transfer to the output signal.
IOE
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
5–7, is clock-period independent. DCD can also be expressed as a
NOT
inst1
CLKH = T/2
Falling Edge A
DFF
inst
Ideal Falling Edge
Clock Period (T)
D
CLRN
PRN
D1
Q
D2
(Figure
Falling Edge B
CLKL = T/2
5–8). Therefore, any DCD
OUTPUT
Altera Corporation
output
April 2011

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