EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 29

EP2S130F1020I5N

Manufacturer Part Number
EP2S130F1020I5N
Description
Manufacturer
Altera
Datasheet

Specifications of EP2S130F1020I5N

Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
742
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant

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0
Figure 2–15. Register Chain within an LAB
Note to
(1)
Altera Corporation
May 2007
The combinational or adder logic can be utilized to implement an unrelated, un-registered function.
Figure
2–15:
Combinational
Combinational
Logic
Logic
See the
information on register chain interconnect.
“MultiTrack Interconnect” on page 2–22
adder0
adder1
adder0
adder1
Note (1)
reg_chain_out
reg_chain_in
Stratix II Device Handbook, Volume 1
D
D
D
D
reg0
reg1
reg0
reg1
From Previous ALM
Within The LAB
To Next ALM
within the LAB
Q
Q
Q
Q
section for more
To general or
To general or
To general or
To general or
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
local routing
local routing
local routing
local routing
Stratix II Architecture
2–21

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