EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 50

• Manufacturer Part Number: EP2S130F1020I5N
• Manufacturer: Altera

Specifications of EP2S130F1020I5N

• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Digital Signal Processing Block
2–42
Stratix II Device Handbook, Volume 1
Table 2–5
DSP block multipliers can optionally feed an adder/subtractor or
accumulator in the block depending on the configuration. This makes
routing to ALMs easier, saves ALM routing resources, and increases
performance, because all connections and blocks are in the DSP block.
Additionally, the DSP block input registers can efficiently implement shift
registers for FIR filter applications, and DSP blocks support Q1.15 format
rounding and saturation.
Figure 2–28
18 × 18-bit multiplier mode.
Note to
(1)
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
Table 2–5. DSP Blocks in Stratix II Devices
Device
Each device has either the numbers of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
Table
shows the number of DSP blocks in each Stratix II device.
shows the top-level diagram of the DSP block configured for
DSP Blocks
2–5:
12
16
36
48
63
96
Multipliers
Total 9 × 9
128
288
384
504
768
96
Note (1)
Total 18 × 18
Multipliers
144
192
252
384
48
64
Altera Corporation
Total 36 × 36
Multipliers
May 2007
12
16
36
48
63
96