EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 80

• Manufacturer Part Number: EP2S130F1020I5N
• Manufacturer: Altera

Specifications of EP2S130F1020I5N

• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

I/O Structure
Figure 2–47. Row I/O Block Connection to the Interconnect
Note to
(1)
2–72
Stratix II Device Handbook, Volume 1
Interconnect
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
LAB Local
Figure
Interconnects
to Adjacent LAB
R4 & R24
Interconnect
2–47:
Direct Link
LAB
io_dataina[3..0]
io_datainb[3..0]
C4 Interconnect
to Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Note (1)
Interconnect
io_clk[7:0]
32
Horizontal
I/O Block
up to Four IOEs
Block Contains
Horizontal I/O
Altera Corporation
32 Data & Control
Signals from
Logic Array (1)
May 2007