EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 36

• Manufacturer Part Number: EP2S130F1020I5N
• Manufacturer: Altera

Specifications of EP2S130F1020I5N

• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

TriMatrix Memory
TriMatrix
Memory
2–28
Stratix II Device Handbook, Volume 1
Column IOE
Row IOE
Maximum performance
True dual-port memory
Simple dual-port memory
Single-port memory
Shift register
ROM
FIFO buffer
Pack mode
Byte enable
Address clock enable
Parity bits
Mixed clock mode
Memory initialization (.mif)
Table 2–2. Stratix II Device Routing Scheme (Part 2 of 2)
Table 2–3. TriMatrix Memory Features (Part 1 of 2)
Memory Feature
Source
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM. Although these memory blocks are different, they can all
implement various types of memory with or without parity, including
true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO
buffers.
blocks.
M512 RAM Block
(32 × 18 Bits)
500 MHz
Table 2–3
v
v
v
v
v
v
v
v
v
shows the size and features of the different RAM
v
v v v v
M4K RAM Block
(128 × 36 Bits)
Destination
550 MHz
v v
v
v
v
v
v
v
v
v
v
v
v
v
(4K × 144 Bits)
M-RAM Block
Altera Corporation
420 MHz
v
v
v
v
v
v
v
v
v
(1)
May 2007