EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 109

• Manufacturer Part Number: EP2S130F1020I5N
• Manufacturer: Altera

Specifications of EP2S130F1020I5N

• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Figure 2–59. Stratix II Receiver Channel
Altera Corporation
May 2007
Up to 1 Gbps
Eight Phase Clocks
+
–
refclk
f
data
Fast
PLL
8
retimed_data
DPA
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed clocks to drive
the SERDES block and/or external pin, and a low-speed clock to drive the
logic array. In addition, eight phase-shifted clocks from the VCO can feed
to the DPA circuitry.
For more information on the fast PLL, see the PLLs in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
The eight phase-shifted clocks from the fast PLL feed to the DPA block.
The DPA block selects the closest phase to the center of the serial data eye
to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of the channel-to-
channel or clock-to-channel skew. The DPA block locks to a phase closest
to the serial data phase. The phase-aligned DPA clock is used to write the
data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment
and SERDES circuitry. Since every channel utilizing the DPA block can
have a different phase selected to sample the data, the synchronizer is
needed to synchronize the data to the high-speed clock domain of the
data realignment and the SERDES circuitry.
DPA_clk
Synchronizer
diffioclk
load_en
D
Q
Data Realignment
Circuitry
Dedicated
Interface
Receiver
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Data to R4, R24, C4, or
direct link interconnect
Regional or
global clock
10
2–101