EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 40

• Manufacturer Part Number: EP2S130F1020I5N
• Manufacturer: Altera

Specifications of EP2S130F1020I5N

• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

TriMatrix Memory
Figure 2–20. M512 RAM Block LAB Row Interface
2–32
Stratix II Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnect
6
M512 RAM Block Local
Interconnect Region
16
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block is used to implement buffers for a wide variety of applications
such as storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains 4,608
RAM bits (including parity bits). M4K RAM blocks can be configured in
the following modes:
■
■
■
■
■
■
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
2
clocks
datain
M512 RAM
LAB Row Clocks
signals
control
Block
address
dataout
Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnect
May 2007