EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 99

• Manufacturer Part Number: EP2S130F1020I5N
• Manufacturer: Altera

Specifications of EP2S130F1020I5N

• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
May 2007
Note to
(1)
Series termination with
calibration
Parallel termination with
calibration
Differential termination
Table 2–17. On-Chip Termination Support by I/O Banks (Part 2 of 2)
On-Chip Termination Support
Clock pins CLK1, CLK3, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip
termination. Clock pins CLK0, CLK2, CLK8, and CLK10 do support differential on-chip termination. Clock pins in
the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination.
Table
2–17:
(1)
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 Class I and II
SSTL-18 Class I and II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.2-V HSTL
SSTL-2 Class I and II
SSTL-18 Class I and II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I and II
1.2-V HSTL
LVDS
HyperTransport technology
I/O Standard Support
Top & Bottom Banks
Stratix II Device Handbook, Volume 1
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v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Stratix II Architecture
Left & Right Banks
v
v
2–91