EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 65

• Manufacturer Part Number: EP2S130F1020I5N
• Manufacturer: Altera

Specifications of EP2S130F1020I5N

• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
May 2007
The Stratix II clock networks can be disabled (powered down) by both
static and dynamic approaches. When a clock net is powered down, all
the logic fed by the clock net is in an off-state thereby reducing the overall
power consumption of the device.
The global and regional clock networks can be powered down statically
through a setting in the configuration (.sof or .pof) file. Clock networks
that are not used are automatically powered down through configuration
bit settings in the configuration file generated by the Quartus II software.
The dynamic clock enable/disable feature allows the internal logic to
control power up/down synchronously on GCLK and RCLK nets and
PLL_OUT pins. This function is independent of the PLL and is applied
directly on the clock network or PLL_OUT pin, as shown in
through 2–39.
1
Enhanced & Fast PLLs
Stratix II devices provide robust clock management and synthesis using
up to four enhanced PLLs and eight fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock-
frequency synthesis. With features such as clock switchover,
spread-spectrum clocking, reconfigurable bandwidth, phase control, and
reconfigurable phase shifting, the Stratix II device’s enhanced PLLs
provide you with complete control of clocks and system timing. The fast
PLLs provide general purpose clocking with multiplication and phase
shifting as well as high-speed outputs for high-speed differential I/O
support. Enhanced and fast PLLs work together with the Stratix II
high-speed I/O and advanced clock architecture to provide significant
improvements in system performance and bandwidth.
The following restrictions for the input clock pins apply:
•
•
•
•
In general, even CLK numbers connect to the inclk[0] port of
CLKCTRL, and odd CLK numbers connect to the inclk[1] port
of CLKCTRL.
Failure to comply with these restrictions will result in a no-fit
error.
CLK0 pin -> inclk[0] of CLKCTRL
CLK1 pin -> inclk[1] of CLKCTRL
CLK2 pin -> inclk[0] of CLKCTRL
CLK3 pin -> inclk[1] of CLKCTRL
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Figures 2–37
2–57