TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 11

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M
DATA SHEET
TXC-03453B
This block also performs SDH/SONET E1 byte AIS detection, which may be carrying an upstream in-band AIS
indication. The TranSwitch PHAST-3N and SOT-3 devices have an option to generate an in-band line/path AIS
indication for the downstream mappers, such as the TL3M, which enables line AIS to be generated without
having to perform an additional pointer AIS detection. In addition, two leads are provided for an out-of-band
upstream AIS indication, using either the PAISn or ISTAn leads.
The POH bytes from the TUG-3 or the STS-1 format are provided at the POH Interface block for external pro-
cessing, if required. Each of the three mappers’ POH interfaces consists of an output data lead (RnPOD), fram-
ing pulse (RnPOF) and a clock signal (RnPOC), where n represents each of three level 3 mappers, starting
with channel 1. All the POH bytes in each of the STS-1s and TUG-3s are supplied, including the B3 byte.
All POH bytes from each of the TUG-3s or STS-1s are also written into Internal RAM block segments for micro-
processor access. In addition, the J1 byte is written into a 64-byte RAM segment on an arbitrary address rotat-
ing basis. Each mapper section also performs POH byte processing, which includes RDI detection, C2
mismatch detection and unequipped detection.
The received O-bits for the DS-3 format are provided at the O-Bit Interface block and are also written into a
2-bit RAM location for microprocessor access. Two reserved bits in the E3 format have been designated as an
O-bit channel, if required. The bits in the RAM location are updated each frame by the TL3M. There is no syn-
chronous relationship between the SDH/SONET frame and the bits written into these RAM locations. The
external interface consists of a serial data lead (RnOCD) and a clock lead (RnOCC).
An Alarm Indication Port block is provided for ring configurations. The alarm indication port consists of a data
lead (RnAID), which is used with the corresponding POH interface framing pulse (RnPOF) and clock signal
(RnPOC). The information on the data lead consists of the REI count and the path RDI alarm summary status.
In a ring configuration, this information is inserted from the mate TL3M mapper channel into the local TL3M
mapper channel G1 byte for transmission.
The Destuff block works in conjunction with the Desync block to remove the stuff columns in the payloads, and
also performs the majority logic voting for the DS3 and E3 formats. The majority voting logic uses the justifica-
tion control bits to determine if the S-bit (or bits) is carrying a stuffing state or data.
The Desync block, using a digital desynchronizer, is responsible for removing the effects on the output of the
DS3 or E3 signals of systemic jitter due to signal mapping and pointer movements. Each of the three desyn-
cronizers has a built-in TranSwitch proprietary pointer leak algorithm, which is transparent to the user. An
option is provided in which the pointer leak rate can be programmed by the host processor. The output has an
average frequency equal to the source frequency and has jitter characteristics that meet both ITU and ANSI
standards.
A line DS3/E3 AIS generator is provided, which enables line AIS to be generated for the various upstream
alarms, such as loss of pointer. A control bit is also provided which enables the microprocessor to send line
AIS independent of the alarm states. An option is provided which enables line AIS to be generated when a
channel is placed in line loopback.
The Output block provides either a positive (RPOSn) and negative (RNEGn) rail line signal, or an NRZ line sig-
nal (RPOSn), and a clock signal (RCLKn). The receive E3 HDB3 and DS3 B3ZS coder operates independent
of the transmitter side. A control bit is provided for inverting the clock output, if required. Also provided is a con-
trol bit which enables the receive data and clock leads to be forced to a high impedance state, independent of
interface type (rail or NRZ) selected. This permits two interfaces from two different devices to be tied together
for ring configurations.
In the transmit direction (towards the Add bus), the Input block supports either a positive (TPOSn) and negative
(TNEGn) rail line signal, or an NRZ line signal (TPOSn), and a clock signal (TCLKn). A control bit enables the
transmit input clock to be inverted. The Input block performs either the E3 HDB3 or DS3 B3ZS decoder func-
tion. Bipolar violations are counted in a 16-bit counter. A choice of bipolar violation sequence detection is also
provided. The rail interface also detects an E3 or DS3 loss of signal. The input clock is also monitored for a
stuck high or low condition. When the NRZ interface is selected, the unused negative rail input lead can be
used to clock in an external loss of signal (LOS) indication from a downstream codec.
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PRELIMINARY TXC-03453B-MB, Ed. 3
September 2003