TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 88

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

September 2003
TL3M
TXC-03453B
PRELIMINARY TXC-03453B-MB, Ed. 3
PER CHANNEL PERFORMANCE COUNTERS AND FIFO LEAK RATE REGISTER DESCRIPTIONS
Some performance counters have 8 bits and some have 16 bits. All 16-bit performance counters allow uninter-
rupted access, without the danger of one byte changing while the other byte is read. To perform a 16-bit read,
the low order byte is read first. This causes a snapshot of the simultaneous value of the high order byte of the
counter to be transferred to a common high order byte at location FFH. The common high order byte should be
read next to complete the count transfer. If another performance counter low order byte is read first, the con-
tents of the common high order byte will change to reflect the high order byte of the performance counter just
read. Counts that occur during the read cycle are held for the counter to be updated afterwards.
All the performance counters can also be configured to be either saturating or non-saturating. When a 1 is writ-
ten to control bit COR (clear on read), the performance counters are configured to be saturating, with the
counters stopping at their maximum count. An 8-bit or 16-bit saturating counter is reset on a microprocessor
read cycle. When a 0 is written to control bit COR, the performance counters are configured to be non-saturat-
ing, and roll over to zero after the maximum count in the counter is reached. The counters are not cleared on a
read cycle.
All the performance counters can be reset simultaneously by writing a 1 to control bit RESETC. This bit is self
clearing, and does not require writing a 0 into this location. See exceptions for XA0H and XA2H below.
All drop-bus related performance counters are inhibited (i.e., will not increment) when one or more of the fol-
lowing alarms occurs:
The performance counters can also be written by the microprocessor. However, when writing to a 16-bit
counter (at locations n, n+1) it is recommended that the low order byte at location n should be written first. The
high order byte can then be written by addressing location n + 1. Since the writes occur in separate cycles,
care must be taken to prevent the low byte from passing FFH and incrementing the high byte before the high
byte is initialized. Writing a low byte equal to 00H will provide the maximum time for the microprocessor to
update the high byte.
Where X=1, 2, or 3, which corresponds to the selected channel:
Address
XA0
XA1
XA2
7-0
7-0
7-0
Bit
- Loss of Drop bus clock alarm (DLOC)
- Loss of Drop bus J1 alarm (DLOJ1)
- AIS detected in the E1 byte (when XALM2AIS = 0)
- When either ISTAn or PAISn lead is high (when XALM2AIS = 1)
- Loss of pointer alarm (TUG-3)
- Path AIS alarm (TUG-3)
Rcv Frame
Symbol
FIFO
Leak
Rate
Cnt
Receive SDH/SONET Frame Counter: Counts the number of received
SDH/SONET frames. This register is not cleared by a software reset and
must be written to 00H to be cleared.
Reserved
FIFO Leak Rate Register: When a value greater then 00H is written into
this location, this number represents the number of frames between con-
secutive leaked bits, in multiples of four frames (i.e., a value of x means
that there are 4x frames between bit leaks).
The value of zero enables an internal TranSwitch pointer leak algorithm.
The algorithm is TranSwitch proprietary. This register is not cleared by a
software reset and must be written to 00H to be cleared.
DATA SHEET
- 88 of 96 -
Description