TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 60

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

September 2003
TL3M
TXC-03453B
PRELIMINARY TXC-03453B-MB, Ed. 3
BOUNDARY SCAN
Introduction
The IEEE 1149.1 standard defines the requirements of a boundary scan architecture that has been specified
by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized scan architecture that provides
observability and controllability for the interface leads of the device. As shown in Figure 37, one cell of a bound-
ary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may
have two cells). The boundary scan capability is based on a Test Access Port (TAP) controller, instruction and
bypass registers, and a boundary scan register bordering the input and output leads. The boundary scan test
bus interface consists of four input signals (Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI)
and Test Reset (TRS)) and a Test Data Output (TDO) output signal. Boundary scan signal timing is shown in
Figure 26.
The TAP controller receives external control information via a Test Clock (TCK) signal and a Test Mode Select
(TMS) signal, and sends control signals to the internal scan paths. The TAP controller is reset by asserting the
TRS lead low for a minimum of 250 nanoseconds. Detailed information on the operation of this state machine
can be found in the IEEE 1149.1 standard. The serial scan path architecture consists of an instruction register,
a boundary scan register and a bypass register. These three serial registers are connected in parallel between
the Test Data Input (TDI) and Test Data Output (TDO) signals, as shown in Figure 37.
The boundary scan function will be reset and disabled by holding lead TRS low. When boundary scan testing is
not being performed the boundary scan register is transparent, allowing the input and output signals to pass to
and from the TL3M device’s internal logic. During boundary scan testing, the boundary scan register may dis-
able the normal flow of input and output signals to allow the device to be controlled and observed via scan
operations.
Boundary Scan Operation
The maximum frequency the TL3M device will support for boundary scan is 10 MHz. The timing diagrams for
the boundary scan interface leads are shown in Figure 26.
The instruction register contains three bits. The TL3M device performs the following six boundary scan test
instructions:
The EXTEST test instruction (000) provides the ability to test the connectivity of the TL3M device to external
circuitry.
The SAMPLE test instruction (001) provides the ability to examine the boundary scan register contents without
interfering with device operation.
The BYPASS test instruction (111) provides the ability to bypass the TL3M boundary scan and instruction reg-
isters.
The IDCODE test instruction (110) activates output on lead TDO of the device ID information.
The MEMBIST test instruction (101) provides a means of testing all internal RAMs. This function is intended for
TranSwitch manufacturing test only.
The HI-Z test instruction (011) places all outputs in a high impedance state.
During the Capture - IR state, a fixed value (101) is loaded into the instruction register.
Boundary Scan Chain
There are 163 scan cells in the TL3M boundary scan chain. Bidirectional signals require two scan cells. Addi-
tional scan cells are used for direction control as needed. A Boundary Scan Description Language (BSDL)
source file is available via the Products page of the TranSwitch World Wide Web site (www.transwitch.com).
DATA SHEET
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