TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 14

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

September 2003
TL3M
TXC-03453B
PRELIMINARY TXC-03453B-MB, Ed. 3
An O-bit interface value or a value written into RAM by the microprocessor is mapped into the two O-bit posi-
tions in the DS3 format. The O-bit interface consists of an output clock signal (TnOCC) and an input data lead
(TnOCD). The relationship between the O-bit channel and the SDH/SONET frame in both directions is asyn-
chronous.
The nine individual POH bytes (except the B3 byte) can be inserted into the TUG-3 or STS-1 POH bytes from
values written to RAM by the microprocessor or from the transmit POH interface. The POH interface consists of
an input data lead (TnPOD), output framing pulse (TnPOF), and an output clock signal (TnPOC), where n rep-
resents each of three level 3 mappers. A control bit enables the POH interface bytes to be written into RAM for
microprocessor access when transmitted. In the case of the G1 byte, the value can also be inserted from the
local receive side or from the alarm indication port. A test mask is provided for the calculated B3 byte, which
permits up to eight errors to be transmitted.
For ring operation, an alarm indication port is provided in the AIP block. The alarm indication port consists of
an input data lead (TnAID), input framing pulse (TnAIF), and input clock signal (TnAIC). The information on the
data lead consists of the REI count, and the path RDI alarm summary status. In ring operation, this information
is inserted into the G1 byte for transmission.
The Add block uses either the add or drop timing signals. Add bus timing is enabled by placing a high on con-
trol lead ABTIM. When Add bus timing is selected, the timing for the two buses, add and drop, is supplied by
separate inputs for add and drop. When Add bus timing is selected, the output Add bus signals consist of byte-
wide data (AD(7-0)), add indication (ADD), and odd parity (APAR). The Add bus input timing signals consist of
a 19.44 MHz clock (ACLK), C1J1 indication (AJ1C1) and a SPE active indication (ASPE). The output Add bus
signals consist of byte-wide data (AD(7-0)), add indication (ADD), and odd parity (APAR). The active low add
indication (ADD) indicates the location of all time slots being added to the Add bus. The Add bus clock is also
monitored for a stuck high or low state when Add bus timing is selected. A bus contention alarm is provided if
more than one channel is assigned to the same TUG-3 or STS-1.
Drop bus timing is enabled by placing a low on control lead ABTIM. When Drop bus timing is selected, the tim-
ing for the Add bus depends upon the Drop bus input signals for operation. When Drop bus timing is selected,
the output Add bus signals consist of byte-wide data (AD(7-0)), add indication (ADD), and odd parity (APAR).
All of the control registers and performance counters, as well as the status and alarm indications, are accessi-
ble via a microprocessor interface. The TL3M supports either Intel or Motorola microprocessor bus interfaces,
with hardware and software interrupts. Mask bits are provided for the latched status and alarm indications, to
control whether each of them will generate an interrupt when active. The counters may be configured as either
rollover or saturating. Saturating counters are cleared automatically when they are read.
For board testing, boundary scan and the ability to force all the output signals to a high impedance state are
provided. For network and device debugging, facility and line loopbacks are provided at the line interfaces.
Each channel also has a PRBS test analyzer and generator (not shown in Figure 2).
DATA SHEET
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