TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 58

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

September 2003
TL3M
TXC-03453B
PRELIMINARY TXC-03453B-MB, Ed. 3
TESTING
Loopbacks
Facility and line loopback capabilities are provided for each channel. Their operations are shown in Figure 36.
Diagrams illustrating these two loopback modes are provided in the Memory Map section at Address XC1, Bits
2 and 1.
Writing a 1 to control bit FLBK (Bit 2) enables facility loopback. When facility loopback is enabled, the internal
DS3/E3 transmit signal becomes the internal receive signal. Either transmit line interface may be used, posi-
tive/negative rail or NRZ.
Line loopback is enabled by writing a 1 to control bit L3LBK (Bit 1). The DS3/E3 receive output becomes the
transmit line input. The receive line output may be positive/negative rail or NRZ. AIS will be sent as the
received data when control bit LLBAIS (bit 0 in register 0C4H) is a 1. When control bit LLBAIS is set to 0,
receive data is provided at the rail or NRZ interface.
Test Generators and Analyzers
Two pseudo-random binary sequence (PRBS) test generators are provided for each channel, one in the
receive direction and the other in the transmit direction, as shown in Figure 36. The generators provide either a
2
common with the PRBS test analyzer. The test sequence of 2
PAT23 (bit 4 in register XC6H). When control bit PAT23 is 0, the pattern is 2
The transmit test generator is enabled by writing a 1 to control bit TPRBS (bit 1 in register XC6H). When
enabled, the transmit test generator inserts the selected pseudo-random pattern in place of the line signal. The
transmit test generator uses the clock signal provided at the Transmit Line Clock (TCLK) input lead in order to
function.
The receive test generator is enabled by writing a 1 to control bit RPRBS (bit 0 in register XC6H). When
enabled, the receive test generator inserts the pseudo-random test pattern in place of the received desynchro-
nized NRZ data.
The test analyzer is enabled by writing a 1 to control bit ENANA (bit 3 in register XC6H). Receive NRZ data is
analyzed when a 0 is written to control bit TXANA (bit 2 in register 0C6H). When a 1 is written to control bit
TXANA, the transmit NRZ data path is monitored. The selection of the test analyzer disables the decoder cod-
ing violation count to the 16-bit CV counter in registers XAEH and XAFH. Instead, this 16-bit counter is config-
ured to count PRBS test analyzer errors when in lock.
15
-1 or 2
23
-1 pseudo-random pattern using a common control bit. The selection of the PRBS pattern is also
DATA SHEET
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23
-1 is selected when a 1 is written into control bit
15
-1.