TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 24

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

September 2003
TL3M
TXC-03453B
PRELIMINARY TXC-03453B-MB, Ed. 3
ADDITIONAL SIGNALS
Symbol
RESET
ABTIM
DAISC
EAISC
PAIS1
PAIS2
PAIS3
ISTA1
ISTA2
ISTA3
TRI
Lead No.
AA10
AA14
AA15
AA16
AB17
AB14
AB15
AB16
AA9
AA8
B21
I/O/P
I
I
I
I
I
I
I
LVTTLp Hardware Reset: A low clears all counters, presets inter-
LVTTLp High Impedance Enable: A low causes all TL3M digital
LVTTL
LVTTL
LVTTL
LVTTL
LVTT
Type
DATA SHEET
- 24 of 96 -
DS3 AIS Clock Input: Input clock for the DS3 AIS gener-
ator. This clock must be present for the DS3 AIS genera-
tor to function. The clock must have the operating line
rate of 44.736 MHz, and a frequency stability of ± 20
ppm. This clock is also used as a backup clock for the
transmit and receive PRBS generators in DS3 applica-
tions, in the event that the transmit or receive DS3 signal
clocks are absent. Clock duty cycle of 45 to 55% is
required. If this clock input is not used, it should be
grounded.
E3 AIS Clock Input: Input clock for the E3 AIS genera-
tor. This clock must be present for the E3 AIS generator
to function. The clock must have the operating line rate of
34.368 MHz, and a frequency stability of ± 20 ppm. This
clock is also used as a backup clock for the transmit and
receive PRBS generators in E3 applications, in the event
that the transmit or receive E3 signal clocks are absent.
Clock duty cycle of 45 to 55% is required. If this clock
input is not used, it should be grounded.
Add Bus Timing Mode: A high placed on this lead
selects the Add bus timing mode. In Add bus timing
mode, Drop and Add buses function with independent
timing. A low placed on this lead selects Drop bus timing
mode. In this mode of operation, the Drop bus signals
provide timing information for the add (transmit) section.
nal logic, and forces the Add bus output signals and line
interfaces to a high impedance state for all three chan-
nels. The reset signal must be low for a minimum of 200
nanoseconds. The bus clocks, line clocks, and micropro-
cessor clock must also be present during the reset sig-
nal. This lead is provided with an internal pull-up resistor.
External Path AIS Indication: A high on this lead may
be used to indicate an external Path AIS has occurred. It
causes the XPAIS status bit (bit 0 in XB4H/XB5H) to be
set to 1. This lead is enabled when control bit XALM2AIS
(bit 7 in XC2H) is a 1. When enabled, the in-band
upstream AIS indication provided via the TOH E1 byte is
disabled. If a lead is not used it should be grounded.
External STS-1 Alarm Indication: A high on this lead may
be used to indicate an external SDH/SONET alarm has
occurred. It causes the XISTAT status bit (bit 1 in XB4H/XB5H)
to be set to 1. If a lead is not used it should be grounded.
outputs and bidirectional leads to be set to a high imped-
ance state for board testing. This lead is provided with an
internal pull-up resistor.
Name/Function