TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 78

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

September 2003
TL3M
TXC-03453B
PRELIMINARY TXC-03453B-MB, Ed. 3
Address
(cont.)
XCA
XC7
XC8
XC9
5-3
7-0
7-2
7-6
4-0
Bit
6
2
1
0
1
0
5
C2 Compare Path Signal Label Compare: The bits in this location are compared
RESETC
Symbol
NOPOH
FIXPTR
REIBLK
RXRST
TXRST
RDI5
TUG-3 Fixed Pointer Generation: A 1 forces a fixed pointer of 0 to be
generated in the transmitted TUG-3 regardless of any pointer movements
(J1 in DC1J1) that may occur on the Drop side when the Drop timing mode
is selected, or if a pointer movement (J1 in AC1J1) takes place when Add
bus timing is selected. When this bit is written with a 0, a pointer movement
on the Add or Drop bus is compensated with an outgoing TUG-3 pointer
movement in the opposite direction.
Reserved: Must be set to zero when register is written.
Transmit Reset: A 1 written into this position resets the transmit section
(Line to SDH/SONET) of the channel. This includes the transmit FIFOs
and internal counters. The channel’s transmitter will remain reset until the
microprocessor writes a 0 into this location.
Receive Reset: A 1 written into this position resets the receive section
(SDH/SONET to Line) of the TL3M device channel. This includes the
receive FIFOs and internal counters. The channel’s receiver will remain
reset until the microprocessor writes a 0 into this location.
Reset Performance Counters: A 1 written into this position resets the
performance counters to 0 for this channel. This bit is self clearing, and
does not require the microprocessor to write a 0 into this location.
against the C2 byte received (register X91H) for a signal label mismatch.
The relationship between the bits of this microprocessor-written byte and
the received C2 byte is shown below:
Reserved: Must be set to zero when register is written.
RDI 5 Consecutive Enable: A 1 enables the detection/recovery algo-
rithms of RDI (bit 5 in the G1 byte) to activate on 5 consecutive matches/
mismatches. A 0 enables the detection/recovery of RDI to activate on 10
consecutive matches/mismatches.
REI (FEBE) Counter Block Count Enable: A 1 configures the REI
(FEBE) counter (register locations XAAH and XABH) to count one or more
REI errors per received G1 byte as one error (block). A 0 configures the
REI counter to count the number of individual errors detected (1 to 8).
Reserved: Must be set to zero when register is written.
No Path Overhead Bytes: When this bit is set to 1, the VC-4 path over-
head time slots of the Add bus data signals AD(7-0) are set to a high
impedance and the ADD signal is high during these time slots. When this
bit is set to 0 the AD(7-0) byte values are set to 00H and the ADD signal is
forced low during the time slots that correspond to the POH bytes.
Reserved: Must be set to zero when register is written.
C2 Compare
Rx C2 Byte
DATA SHEET
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1
7
2
6
3
5
Description
4
4
5
3
6
2
7
1
8
0