TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 25

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

DIGITAL DESYNCHRONIZERS
Symbol
SUBD1
SUBD2
SUBD3
GRD1
GRD2
GRD3
VRD1
DBS1
VRD2
DBS2
VRD3
DBS3
DF1A
DF1B
DF2A
DF2B
DF3A
DF3B
DF1E
DF2E
DF3E
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Lead No.
AA19
W22
M22
M21
R22
R21
Y22
N21
P19
N20
V22
U20
U22
K22
N22
U21
B19
H20
L22
L21
L20
I/O/P
O
I
I
I
I
I
I
I
LVCMOS
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Type
4mA
DATA SHEET
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Digital Desynchronizer PLL External Capacitor -
Channel 1: An external 1.0 F ± 10% capacitor (alter-
nate capacitor value 4.7 F) is connected between the
two leads, as shown in the PLL connections diagram
(Figure 27).
Digital Desynchronizer PLL External Capacitor -
Channel 2: An external 1.0 F ± 10% capacitor (alter-
nate capacitor value 4.7 F) is connected between the
two leads, as shown in the PLL connections diagram
(Figure 27).
Digital Desynchronizer PLL External Capacitor -
Channel 3: An external 1.0 F ± 10% capacitor (alter-
nate capacitor value 4.7 F) is connected between the
two leads, as shown in the PLL connections diagram
(Figure 27).
Digital Desynchronizer PLL Bias Components -
Channel 1: An external 30.1 k 1% resistor is connected
between the GRD1 lead and the DBS1 lead, as shown in
the PLL connections diagram (Figure 27). VRD1 should
be left unconnected.
Digital Desynchronizer PLL Bias Components -
Channel 2: An external 30.1 k 1% resistor is connected
between the GRD2 lead and the DBS2 lead, as shown in
the PLL connections diagram (Figure 27). VRD2 should
be left unconnected.
Digital Desynchronizer PLL Bias Components -
Channel 3: An external 30.1 k 1% resistor is connected
between the GRD3 lead and the DBS3 lead, as shown in
the PLL connections diagram (Figure 27). VRD3 should
be left unconnected.
Digital Desynchronizer Dedicated Substrate Connec-
tions. These leads are normally connected to ground.
FIFO Reset Indication. These leads are used to indicate
a reset condition from their corresponding desynchro-
nizer. The indication will be high for a minimum of 125
microseconds and a maximum of 250 microseconds for
any of the following
- Hardware Reset (RESET lead goes low)
- RESET (bit 0 in 0C7H) is a 1
- RESETn (0C7H) is set to 1 for the corresponding
- FIFO overflow or underflow
channel.
Name/Function
PRELIMINARY TXC-03453B-MB, Ed. 3
TXC-03453B
September 2003
TL3M