TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 82

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

September 2003
TL3M
TXC-03453B
PRELIMINARY TXC-03453B-MB, Ed. 3
Address
(cont.)
XB4
XB5
XB6
XB7
5-0
7-0
Bit
2
1
0
7
6
7
6
5
4
3
2
1
0
PLLLOC
AISLOC
Symbol
RPLOC
RFRST
TPLOC
XISTAT
L3ERR
TFRST
LOVFL
XPAIS
OOL
AIS Loss Of Clock Detected: The AIS selected (DS3 or E3) is monitored
for a stuck high or stuck low condition, An unlatched AIS LOC indication
occurs when the EAIS or DAIS clock is stuck high or low for approximately
225 ns. Recovery occurs within 100 ns of the first EAIS or DAIS clock cycle
transition. ACLK (lead P1), when ABTIM (lead B21) is asserted or DCLK
(lead K3), when ABTIM is unasserted, must be present for this alarm to
function.
External STS-1 Alarm: This unlatched alarm indicates that the input on the
lead labeled ISTAn is high. It may be used to indicate an external alarm
condition (e.g., LOP). Detection and recovery follow ISTAn immediately.
External Path AIS: This unlatched alarm indicates that the input on the
lead labeled PAISn is high. It may be used to indicate an external alarm
condition (e.g., path AIS). Detection and recovery follow PAISn immediately.
Reserved: Must be set to zero when register is written.
Reserved:
This register contains latched bits that correspond to the unlatched bits 5-0
in register XB4H. These latched bits are reset to 0 when they are read.
Analyzer Error Indication: This unlatched alarm indicates that the 2
2
to ENANA (bit 3, in XC6H) enables the analyzer. When control bit ENANA is
a 0, the analyzer and alarm are disabled.
Receive Leak FIFO Overflow/Underflow Alarm: This unlatched alarm
indicates that the receive FIFO has either underflowed or overflowed. The
FIFO automatically resets to a preset value on the occurrence of the alarm.
Receive FIFO Reset Indication: This unlatched alarm indicates that either
the leak FIFO or the receive dejitter FIFO has been reset. This may occur
because of a FIFO overflow/underflow alarm, or when the receive section
has been reset by writing a 1 to control bit RXRST, or upon hardware reset.
Transmit FIFO Reset Indication: This unlatched alarm indicates that the
transmit FIFO has been reset. This may occur because of a FIFO overflow/
underflow alarm, or when the transmitter has been reset by writing a 1 to
control bit TXRST, or upon hardware or software reset.
Desynchronizer Phase Lock Loop Loss Of Clock: This unlatched alarm
indicates the internal PLL has experienced loss of clock for approximately
225 ns. Recovery occurs within 100 ns of the first PLL clock transition. ACLK
(lead P1), when ABTIM (lead B21) is asserted or DCLK (lead K3), when
ABTIM is unasserted, must be present for this alarm to function.
Loss of Transmit PLL Clock: This unlatched alarm indicates that the inter-
nal transmit PLL clock has been stuck high or low for approximately 250 ns.
Recovery occurs within 100 ns of the first PLL clock transition. DCLK (lead
K3) must be present for this alarm to function.
Loss of Receive PLL Clock: This unlatched alarm indicates that the inter-
nal receive PLL clock has been stuck high or low for approximately 225 ns.
Recovery occurs within 100 ns of the first PLL clock transition. ACLK (lead
P1), when ABTIM (lead B21) is asserted or DCLK (lead K3), when ABTIM
is unasserted, must be present for this alarm to function.
Analyzer Out of Lock: This unlatched alarm indicates that the PRBS test
analyzer, when enabled, is out of lock.
This register contains latched bits that correspond to the unlatched bits in
register XB6H. These latched bits are reset to 0 when they are read.
23
-1 PRBS test analyzer has detected an error when enabled. A 1 written
DATA SHEET
- 82 of 96 -
Description
15
-1 or