TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 19

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TXC-03453BROG

Manufacturer Part Number
TXC-03453BROG
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-03453BROG

Screening Level
Industrial
Package Type
BGA
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TXC-03453BROGA
Manufacturer:
TRANSWITCH
Quantity:
5
LINE INTERFACE
Where n represents the channel (mapper) number, for channels 1 through 3.
Symbol
Symbol
RPOS1
RPOS2
RPOS3
RNEG1
RNEG2
RNEG3
APAR
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Lead No.
Lead No.
AA21
W20
G20
D21
E20
F22
P4
I/O/P*
I/O/P
O (T)
O (T)
O(T)
LVCMOS
LVCMOS
LVCMOS
Type
Type
4mA
4mA
4mA
DATA SHEET
- 19 of 96 -
Add Bus Parity Bit: This output bit represents an odd
parity calculation for each data byte that is mapped to the
Add bus in the add timing and Drop bus timing modes.
This lead is forced to a high impedance state when
Receive Line Positive Rail/NRZ Data for Channel n:
When control bit CODE (bit 6 in XC1H) is a 0 for the cor-
responding channel, this lead provides the received NRZ
output for the 44.736 (DS3) or 34.368 Mbit/s (E3) asyn-
chronous line data. When control bit CODE is a 1, a pos-
itive rail output signal is provided. This lead is forced to a
high impedance state when
Receive Negative Rail Data for Channel n: When con-
trol bit CODE (bit 6 in XC1H) is a 0, the corresponding
lead is set to low. When control bit CODE is a 1, a nega-
tive rail output is provided. This lead is forced to a high
impedance state when
- Data is not present
- Hardware or software reset occurs
- Drop Bus Loss Of Clock (DLOC) occurs when the
- When control bit ADDEN (bit 1 in 0C2H) is set to 0.
- Control bit L3EN (bit 0 in 0C2H) is set to 0
- Control bit L3OEN (bit 0 in XC2H) is set to 0 for the
- Hardware reset (lead RESET) or software reset
- RESETn (bits 1-3 in 0C7H) is set to 1 for the corre-
- Control bit L3EN (bit 0 in 0C2H) is set to 0
- Control bit L3OEN (bit 0 in XC2H) is set to 0 for the
- Hardware reset (lead RESET) or software reset
- RESETn (bits 1-3 in 0C7H) is set to 1 for the corre-
Drop bus timing mode is selected (ABTIM lead is
low)
corresponding channel
(RESETS, bit 0 in 0C7H) occurs
sponding channel.
corresponding channel
(RESETS, bit 0 in 0C7H) occurs
sponding channel.
Name/Function
Name/Function
PRELIMINARY TXC-03453B-MB, Ed. 3
TXC-03453B
September 2003
TL3M

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