TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 79

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

COMMON STATUS BIT DESCRIPTIONS
Status bits report the condition of alarms as both current status (unlatched) and event record (latched) bit posi-
tions. The unlatched bit goes to 1 for only as long as the alarm persists, while a latched bit is set to 1 upon the
first occurrence of the alarm and it remains active until its register is read, when it is reset to 0. Only latched
bits that are read as 1 are reset, to preserve alarms which occur during the read operation. If a current alarm is
present after this reset, the corresponding latched bit will be set to 1 again. The unlatched bits occupy
even-numbered registers. Their corresponding latched bits are in the same bit positions of the following
odd-numbered register. Latched bits activate an interrupt while set to 1, unless their mask bit is set to 0.
PER CHANNEL STATUS BIT DESCRIPTIONS
The per channel status bits perform in the same way as described above for common status bits.
Where X=1, 2, or 3, which corresponds to the selected channel:
Address
Address
XB0
0B0
0B1
0B6
0B7
Bit
7-3
7-0
6-0
7-0
Bit
Proprietary TranSwitch Corporation Information for use Solely by its Customers
2
1
0
7
7
6
Symbol
ADBCN
Symbol
DLOJ1
DLOC
INT3
INT2
INT1
Reserved
Interrupt Indication (INTn) for Channel n: A 1 indicates that channel n
has at least one latched alarm set to 1 that is not masked from causing an
interrupt. This bit provides information that enables the microprocessor to
read the status bits associated with that channel and determine which
alarms have occurred.
This register contains latched bits that correspond to the unlatched bits in
register 0B0H. These latched bits are reset to 0 when they are read.
Add Bus Contention Indication: A 1 indicates that more than one channel
is attempting to drive the Add bus at the same time. This is usually due to
the fact that more than one channel has been assigned to the same TUG-3
or STS-1 in the add direction.
Reserved
This register contains latched bits that correspond to the unlatched bits in
register 0B6H. These latched bits are reset to 0 when they are read.
Drop Bus Loss Of Clock Alarm: An unlatched loss of clock alarm occurs
when the input Telecom Bus Drop bus clock has been stuck high or low for
approximately 225 ns. Recovery occurs within 100 ns of the first bus clock
transition. ACLK (lead P1), when ABTIM (lead B21) is asserted or DCLK
(lead K3), when ABTIM is unasserted, must be present for this alarm to
function.
Drop Bus Loss of J1: An unlatched Drop bus loss of J1 alarm occurs
when:
Recovery occurs when the J1 pulse is detected in the same location for 8
consecutive frames.
- 8 consecutive new J1 positions have been detected or
- J1 is stuck low for 8 consecutive frames or
- J1 is stuck high for 8 consecutive bytes or
- 8 J1 pulses are received in one frame.
DATA SHEET
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Description
Description
PRELIMINARY TXC-03453B-MB, Ed. 3
TXC-03453B
September 2003
TL3M