TXC-03453BROG Transwitch Corporation, TXC-03453BROG Datasheet - Page 18

• Manufacturer Part Number: TXC-03453BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-03453BROG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

September 2003
TL3M
TXC-03453B
PRELIMINARY TXC-03453B-MB, Ed. 3
ADD BUS INTERFACE
Symbol
AD(7-0)
AC1J1
ASPE
ACLK
ADD
M1, M3, M2, N1
K1, L3, L2, L1,
Lead No.
P1
N3
N2
P2
I/O/P
O(T)
O
I
I
I
LVCMOS
LVCMOS
LVTTL
LVTTL
LVTTL
Type
4mA
4mA
DATA SHEET
- 18 of 96 -
Add Bus Data Byte: 19.44 Mbytes/s byte-wide data that
corresponds to the time slots that are placed on the Add
bus by the TL3M. Lead K1 is AD7. The first bit transmit-
ted (MSB) corresponds to bit 7. These leads are forced to
a high impedance state when:
Add Bus Clock: This input clock operates at 19.44 MHz.
The add clock is used when the Add bus timing mode is
selected (ABTIM lead is high). Add bus byte-wide data
(AD(7-0)), the ASPE signal, and the AC1J1 signal are
clocked in on its falling edges. The parity (APAR) signal,
and add indicator (ADD) are clocked out on its rising
edges. This lead is disabled, and should be grounded,
when the drop timing mode is selected (ABTIM lead is
low).
Add Bus SPE Indicator: An input signal that must be
high to indicate the STM-1 VC-4 period, and each of the
three STS-3/STS-1 SPE periods, when Add bus timing is
selected. This lead is disabled, and should be grounded,
when the drop timing mode is selected (ABTIM lead is
low).
Add Bus C1 and J1 Indicator: The C1 pulse is an active
high, one clock cycle-wide (ACLK) input timing pulse that
identifies the location of the first C1 (J0) time slot in the
STM-1 or STS-3 frame. A single J1 pulse, also one clock
cycle wide, identifies the starting location of the J1 byte in
the STM-1 VC-4 signal. Three J1 pulses are used to
identify the starting location of the J1 bytes in each of the
three STS-3 STS-1 SPEs. This lead will carry only J1
pulse information when the DC1 lead is used. This lead is
disabled, and should be grounded, when the drop timing
mode is selected (ABTIM lead is low).
Add Indicator: An active low signal that identifies the
position of the TUG-3 and STS-1 bytes that are being
mapped to the Add bus. This signal will be high when
- Data is not present
- Hardware or software reset occurs
- Drop Bus Loss Of Clock (DLOC) occurs when the
- When control bit ADDEN (bit 1 in 0C2H) is set to 0.
- Data is not present
- Hardware or software reset occurs
- Drop Bus Loss Of Clock (DLOC) occurs when the
- When control bit ADDEN (bit 1 in 0C2H) is set to 0.
Drop bus timing mode is selected (ABTIM lead is
low)
Drop bus timing mode is selected (ABTIM lead is
low)
Name/Function