UPD75518 NEC, UPD75518 Datasheet - Page 100

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

IRQCSI0
100
4.8.5 Serial Interface (Channel 0) Operation
(1) Operation halt mode
(2) Three-wire serial I/O mode operations
SCK0
SO0
SI0
The operation halt mode is used when serial transfer is not performed. This mode reduces power
consumption.
The shift register 0 does not perform shift operation in this mode, so the shift register can be used as a
normal 8-bit register. When the RESET signal is entered, the operation halt mode is set.
The P02/SO0/SB0 pin and P03/SI0/SBI pin function as input-only port pins. The P01/SCK0 pin can be used
as an input port pin by setting the serial operation mode register 0.
The three-wire serial I/O mode is compatible with other modes used in the 75X series, PD7500 series,
and 78K series.
Communication is performed using three lines: Serial clock (SCK0), serial output (SO0), and serial input
(SI0).
(a) Communication operation
The three-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by
bit in phase with the serial clock.
The shift register performs shift operation on the falling edge of the serial clock (SCK0). Transmit data
is latched on the SO0 latch, and is output on the SO0 pin. Receive data applied to the SI0 pin is latched
in the shift register 0 on the rising edge of SCK0.
When eight bits have been transferred, shift register 0 operation automatically terminates setting the
interrupt request flag (IRQCSI0).
Execution of instruction that writes data to SIO0 (Transfer start request)
Fig. 4-44 Timing of Three-Wire Serial I/O Mode
1
Transfer is started in phase with falling edge of SCK0.
DO7
DI7
2
DO6
DI6
3
DO5
DI5
4
DO4
DI4
5
DO3
DI3
6
DO2
DI2
7
DO1
DI1
Completion of transfer
PD75518(A)
8
DO0
DI0