UPD75518 NEC, UPD75518 Datasheet - Page 111

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

4.8.7 Manipulation of SCK0 Pin Output
in addition to normal serial clock output.
SB1 pin is controlled by manipulating the RELT and CMDT bits of SBIC.)
1
2
The SCK0/P01 pin has a built-in output latch, so that this pin allows static output by software manipulation
The number of SCK0s can be software-set arbitrarily by manipulating the P01 output latch. (The SO0/SB0/
The procedure for manipulating SCK0/P01 pin output is explained below.
Example To output one clock cycle on the SCK0/P01 pin by software
The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to 1.
Cautions 1. During normal serial transfer, the P01 output latch must be set to 1.
Set serial operation mode register 0 (CSIM0) (SCK0 pin: output mode). When serial transfer is
halted, SCK0 from the serial clock control circuit is set to 1.
Manipulate the P01 output latch by using a bit manipulation instruction.
P01/SCK0
SEL
MOV
MOV
CLR1
SET1
2. The P01 output latch cannot be addressed by specifying PORT0.1 (as described below). The
address of the latch (0FF0H.1) must be coded in the operand of an instruction directly.
However, MBE = 0 (or MBE = 1, MBS = 15) must be specified before the instruction is
executed.
CLR1 PORT0.1
SET1 PORT0.1
CLR1 0FF0H.1
SET1 0FF0H.1
MB15
XA, #10000011B ; SCK0 (f
CSIM0, XA
0FF0H.1
0FF0H.1
When CSIE0=1 and CSIM01
and CSIM00 are not 00
Fig. 4-53 SCK0/P01 Pin Circuit Configuration
Not allowed
Allowed
; or CLR1 MBE
; SCK0/P01
; SCK0/P01
To internal circuit
X
/2
3
), output mode
0
1
Address
FF0H.1
P01
output
latch
SCK0
From the serial clock
control circuit
PD75518(A)
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