UPD75518 NEC, UPD75518 Datasheet - Page 127

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

5.2 HARDWARE OF THE INTERRUPT CONTROL CIRCUIT
(1) Interrupt request flag and interrupt enable flag
The following nine interrupt request flags (IRQ
INT0 interrupt request flag (IRQ0)
INT1 interrupt request flag (IRQ1)
INT2 interrupt request flag (IRQ2)
INT4 interrupt request flag (IRQ4)
BT interrupt request flag (IRQBT)
The interrupt request flag is set to 1 when an interrupt request is issued, and is automatically cleared to
0 when the CPU is interrupted. Since the IRQBT and IRQ4 share the vector address, the clear operation
varies. (See Section 5.5.)
The following nine interrupt request flags (IE
available.
INT0 interrupt enable flag (IE0)
INT1 interrupt enable flag (IE1)
INT2 interrupt enable flag (IE2)
INT4 interrupt enable flag (IE4)
BT interrupt enable flag (IEBT)
When an interrupt request flag is set, the interrupt enable flag corresponding to that interrupt request flag
enables the request interrupt. When an interrupt request flag is cleared, the interrupt enable flag
corresponding to that interrupt request flag disables the interrupt.
When an interrupt request flag is set and its corresponding interrupt enable flag enables the requested
interrupt, a vectored interrupt request (VRQn) is issued. This signal is also used for releasing the standby
mode.
The interrupt request flags and interrupt enable flags are manipulated with bit manipulating instructions
and 4-bit memory manipulation instructions. When a bit manipulation instruction is used, the flags can
always be manipulated directly irrespective of the MBE setting. The interrupt enable flags are manipulated
with EI IE
flag.
Example EI
When an interrupt request flag is set with an instruction, a vectored interrupt is executed irrespective of
whether an interrupt occurs.
When a RESET signal is generated, an interrupt request flag and its corresponding interrupt enable flag
are cleared and all interrupts are disabled.
DI
SKTCLR IRQCSI0 ; Skips and clears the interrupt request flag if IRQCSI0 is 1.
and DI IE
IE0
IE1
instructions. An SKTCLR instruction is normally used to test an interrupt request
; Enables INT0.
; Disables INT1.
Serial interface interrupt request flag (IRQCSI0)
Timer/event counter 0 interrupt request flag (IRQT0)
Timer/pulse generator interrupt request flag (IRQTPG)
Clock timer interrupt request flag (IRQW)
Serial interface enable flag (IECSI0)
Timer/event counter 0 interrupt enable flag (IET0)
Timer/pulse generator interrupt enable flag (IETPG)
Clock timer interrupt enable flag (IEW)
) corresponding to the interrupt sources are available.
) corresponding to the interrupt request flags are
PD75518(A)
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