UPD75518 NEC, UPD75518 Datasheet - Page 142

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

142
7. RESET FUNCTION
7-1. Fig. 7-1 shows the timing of reset operation.
Program counter (PC)
PSW
Data memory (RAM)
General registers (X, A, H, L, D, E, B, C)
Bank select register (MBS, RBS)
Stack pointer (SP)
Stack bank select register (SBS)
Basic interval
timer
Timer/event
counter
Timer/pulse
generator
Watch timer
The PD75518(A) is reset by RESET signal input. When reset, the hardware is initialized as indicated in Table
Note A wait time is 31.3 ms when operating at 4.19 MHz.
Note RESET signal input causes data at addresses 0F8H-0FDH in data memory to be undefined.
Carry flag (CY)
Skip flags (SK0 to SK2)
Interrupt status flags (IST0, IST1)
Bank enable flags (MBE, RBE)
RESET input
Counter (BT)
Mode register (BTM)
Counter (T0)
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT F/F
Modulo registers (MODH, MODL)
Mode register (TPGM)
Mode register (WM)
Hardware
Table 7-1 Statuses of the Hardware after a Reset (1/2)
Fig. 7-1 Reset Operation by RESET input
Operating mode or
standby mode
Internal reset operation
RESET input in a standby mode
Low-order 6 bits at address 0000H
in program memory are set in PC
bits 13 to 8, and the data at address
0001H are set in PC bits 7 to 0.
Held
0
0
Bit 6 at address 0000H in pro-
gram memory is set in RBE, and
bit 7 is set in MBE.
Held
Held
0, 0
Undefined
Undefined
Undefined
0
0
FFH
0
0, 0
Held
0
0
Note
(approximately 21.8 ms/6.0 MHz)
HALT mode
Wait
Low-order 6 bits at address 0000H
in program memory are set in PC
bits 13 to 8, and the data at address
0001H are set in PC bits 7 to 0.
Undefined
0
0
Bit 6 at address 0000H in pro-
gram memory is set in RBE, and
bit 7 is set in MBE.
Undefined
Undefined
0, 0
Undefined
Undefined
Undefined
0
0
FFH
0
0, 0
Held
0
0
RESET input during operation
Note
Operating mode
PD75518(A)