UPD75518 NEC, UPD75518 Datasheet - Page 72

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

72
(4) Operation mode of the timer/event counter
The timer/event counter operates in the count operation disable mode or in the count operation mode,
depending on the setting of the mode register.
The following operations are possible, regardless of the setting of the mode register:
1 P13/TI0 pin signal input and test
2 Output of the timer out F/F status to the PTO0
3 Setting of the modulo register (TMOD0)
4 Reading from the count register (T0)
5
(a) Count operation disable mode
Address
FA2H
Setting, clearing, and testing of the interrupt request flag (IRQT0)
This mode is set when bit 2 of TM0 is set to 0. In this mode, count operation is not performed because
count pulse (CP) supply to the count register is stopped.
TOE0
3
Fig. 4-26 Format of the Timer/Event Counter Output Enable Flag
Timer/event counter output enable flag (W)
0
1
Disables
Enables
PD75518(A)