UPD75518 NEC, UPD75518 Datasheet - Page 135

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

5.4 MULTIPLE INTERRUPT PROCESSING CONTROL
(1) Multiple interrupt processing by a high-order interrupt
IST1
The PD75518(A) can handle multiple interrupts by either of the following methods.
0
0
1
1
In this method, the PD75518(A) selects an interrupt source among multiple interrupt sources, enabling
double interrupt processing.
That is, the high-order interrupt specified by the interrupt priority specification register (IPS) is enabled
when the processing status is 0 or 1. Other interrupts (interrupts lower than the specified high-order
interrupt) are enabled only when the status is 0. (See Fig. 5-6 and Table 5-3.)
IST1 and IST0 are saved with the remaining PSW in the stack memory when an interrupt is accepted and
the status of IST0 and IST1 changes to a status one level higher. When an RETI instruction is executed,
the former values of IST0 and IST1 are returned.
IST0
0
1
0
1
Interrupt is disabled.
Low- or high-order
interrupt occurrence
Status 0
Status 1
Status 2
Interrupt is enabled.
This status is disabled.
Processing
status
Fig. 5-6 Multiple Interrupt Processing by a High-Order Interrupt
IPS setting
Table 5-3 Interrupt Processing Statuses of IST1 and IST0
Is processing the normal
program.
Is processing a low- or high-
order interrupt.
Is processing a high-order
interrupt.
Normal
processing
(Status 0)
CPU operation
High-order
interrupt
occurrence
Low- or high-order
interrupt processing
(Status 1)
All
Only high-order interrupts
No
Interrupts that can be accepted
High-order
interrupt
processing
(Status 2)
PD75518(A)
After acceptance
IST1
0
1
–
IST0
1
0
–
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