UPD75518 NEC, UPD75518 Datasheet - Page 93
UPD75518
Manufacturer Part Number
UPD75518
Description
4 BIT SINGLE-CHIP MICROCOMPUTER
Manufacturer
NEC
Datasheet
1.UPD75518.pdf
(180 pages)
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(3) Shift register (SIO0)
Fig. 4-37 shows the configuration of peripheral hardware of shift register 0. SIO0 is an 8-bit register which
performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock.
Serial transfer is started by writing data to SIO0.
In tansmission, data written to SIO0 is output on the serial output (SO0) or serial data bus (SB0/SB1). In
reception, data is read from the serial input (SI0) or SB0/SB1 into SIO0.
Data can be read from or written to SIO0 by using an 8-bit manipulation instruction.
When the RESET signal is entered during operation, the value of SIO0 is undefined. When the RESET signal
is entered in the standby mode, the value of SIO0 is preserved.
Shift operation is stopped after 8-bit transmission or reception is completed.
The timing for reading SIO0 and start of serial transfer (writing to SIO0) is as follows:
• When the serial interface operation enable/disable bit (CSIE0) = 1. However, the case where CSIE0 is
• When the serial clock is masked after 8-bit serial transfer
• SCK0 is high.
set to 1 after data is written to the shift register 0 is excluded.
N-ch open-drain output
CSIM0
Shift register (SIO0)
Shift clock
Fig. 4-37 Peripheral Hardware of Shift Register 0
Internal bus
Address
comparator
D
SET
BUSY/ACK
CLK
PD75518(A)
CLR
Q
SO0 latch
RELT
CMDT
93
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