UPD75518 NEC, UPD75518 Datasheet - Page 139

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

(A STOP instruction sets bit 3 of PCC, and a HALT instruction sets bit 2 of PCC.) A STOP instruction or HALT
instruction must always be followed by an NOP instruction.
the time when PCC is rewritten to the time when the CPU clock signal is changed. When changing an operation
clock pulse before the standby mode or a CPU clock signal after the standby mode is released, it is necessary
to rewrite PCC and set the standby mode after the number of machine cycles required to change the CPU clock
pulse elapses.
including general registers, flags, mode registers, and output latches, are retained.
6.2 RELEASE OF THE STANDBY MODES
signal that is enabled with the interrupt enable flag. Fig. 6-1 shows how the STOP and HALT modes are
released.
A STOP instruction is used to set the STOP mode, and a HALT instruction is used to set the HALT mode.
When changing a CPU operation clock pulse with the low-order two bits of PCC, a time lag may occur from
In a standby mode, the contents of all registers and data memory that are stopped during the standby mode,
Cautions 1. When the STOP mode is set, the X1 input is internally connected to GND (GND potential) to
The STOP mode and HALT mode are released by a RESET input or the generation of an interrupt request
2. Reset all the interrupt request flags before setting the standby mode.
suppress leakage at the crystal oscillator circuitry. This means that the STOP mode cannot
be used with a system that uses an external clock.
If an interrupt source whose interrupt request flag and interrupt enable flag are both set exists,
the initiated standby mode is released immediately after it is set (see Fig. 5-1). When the STOP
mode is set, however, the PD75518(A) enters the HALT mode immediately after the STOP
instruction is executed, then returns to the operation mode after the wait time specified by
the BTM register has elapsed.
PD75518(A)
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