UPD75518 NEC, UPD75518 Datasheet - Page 128

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

128
(2) Configurations of INT0, INT1, and INT4 pins
Interrupt
request flag
IRQBT
IRQ4
IRQ0
IRQ1
IRQCSI0
IRQT0
IRQTPG
IRQW
IRQ2
(a) As shown in Fig. 5-2 (a), INT0 is configured as an external interrupt pin that enables detection edge
(b) As shown in Fig. 5-2 (b), INT1 is configured as an external interrupt pin that enables detection edge
(c) As shown in Fig. 5-2 (c), INT4 is configured as an external interrupt pin that enables detection of both
Fig. 5-3 (a) shows the format of IM0. A 4-bit memory manipulation instruction is used to set IM0. A
Note t
selection.
In addition, the INT0 pin is provided with a noise elimination function using a sampling clock. The
noise eliminator eliminates pulses narrower than two-sampling-clock-cycle pulses (2t
f
INT0 has two sampling clocks
of the edge detection mode register (See Fig. 5 - 3(a).)
Bits 0 and 1 (IM00 and IM01) of the edge detection mode register are used to select a detection edge.
RESET signal occurrence clears all bits to 0, and a rising edge is specified to be detected.
selection.
The edge detection mode register (IM1) is used to select a detection edge.
Fig. 5-3 (b) shows the format of IM1. A 4-bit memory manipulation instruction is used to set IM1. A
RESET signal occurrence clears all bits to 0, and a rising edge is specified to be detected.
rising and falling edges.
Cautions 1. Since the INT0 input is sampled with a clock, INT0 does not operate in a standby mode.
X
) as noise and accepts pulses wider than as interrupt signals.
Set by a reference time interval signal from the basic interval timer.
Set by a detected rising or falling edge of an INT4/P00 pin input signal.
Set by a detected edge of an INT0/P10 pin input signal. The detection edge is specified
by the INT0 mode register (IM0).
Set by a detected edge of an INT1/P11 pin input signal.
by the INT1 mode register (IM1).
Set by a serial data transfer completion signal for the serial interface.
Set by a match signal from timer/event counter 0.
Set by a match signal from the timer/pulse generator.
Set by a signal from the clock timer.
Set by a detected rising edge of an INT2/P12 pin input signal, or a detected falling edge
of one of a KR0/P60-KR7/P73 pin input signals.
CY
represents a cycle time.
2. Input a pulse wider than two sampling clock cycles to the INT0/P10 pin. Otherwise, the
pulse is suppressed as noise by the noise eliminator when the pin is used as a port.
Table 5-2 Set Signals of Interrupt Request Flags
Set signal of interrupt request flag
and f
X
/64, either of which can be selected according to bit 3 (IM03)
The detection edge is specified
CY
Interrupt
enable flag
Note
PD75518(A)
IEBT
IE4
IE0
IE1
IECSI0
IET0
IETPG
IEW
IE2
or 128/