UPD75518 NEC, UPD75518 Datasheet - Page 69

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

4.6 TIMER/EVENT COUNTER
(1) Configuration of the timer/event counter
(2) Functions of the timer/event counter
(3) Timer/event counter mode register (TM0) and timer/event counter output enable flag (TOE0)
The PD75518(A) contains one channel of timer/event counter, which is configured as shown in Fig.
4-24.
The timer/event counter has the following functions.
The timer/event counter mode register (TM0) is an 8-bit register for controlling the timer/event counter.
Fig. 4-25 shows its format.
An 8-bit memory manipulation instruction is used to set the timer/event counter mode register.
Bit 3 is the timer start bit, and can be set independently of the other bits. Bit 3 is automatically reset to
0 when the timer starts operation.
The generation of a RESET signal clears all bits to 0.
The timer/event counter output enable flag (TOE0) enables or disables output of the timer out F/F (TOUT
F/F) status to the PTO0 pin.
The timer out F/F (TOUT F/F) is inverted by a match signal transmitted from the comparator.
The timer out F/F is reset when an instruction sets bit 3 of the timer mode register (TM0).
The generation of a RESET signal clears the TOE0 and TOUT F/F to 0.
(a) Programmable interval timer operation
(b) Output of a square wave at a given frequency to the PTO0 pin
(c) Event counter operation
(d) Frequency divider operation that divides TI0 pin input by N and outputs the result to the PTO0 pin
(e) Supply of serial shift clock signal to a serial interface circuit
(f) Function of reading the state of counting
Examples 1. The timer is started in the interval timer mode with CP = 4.09 kHz.
2.
SEL
MOV
MOV
The timer is restarted according to the setting of the timer/event counter mode register.
SEL
SET1
MB15
XA, #01001100B
TM0, XA
MB15
TM0.3
; or CLR1 MBE
; TM0
; or CLR1 MBE
; TM0.bit3
4CH
1
PD75518(A)
69