UPD75518 NEC, UPD75518 Datasheet - Page 105

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

SB0/SB1
SB0/SB1
SB0/SB1
Address transfer
Command transfer
Data transfer
(b) Communication operation
SCK0
SCK0
SCK0
In the SBI mode, the master usually selects a slave device to communicate with from multiple devices
by outputting the address of the slave in the serial bus.
After selecting a device to communicate with, the master exchanges commands and data with the
slave device, thus establishing serial communication.
Fig. 4-49 to 4-52 show the timing charts of data communication operations.
In the SBI mode, the shift register 0 performs shift operation on the falling edge of the serial clock
(SCK0). Transmit data is held on the SO0 latch, and is output on the SB0/P02 or SB1/P03 pin starting
with the MSB. Receive data applied to the SB0 (or SB1) pin is latched in the shift register 0 on the
rising edge of SCK0.
Bus release signal
Fig. 4-48 Timing of SBI Transfer
Command signal
A7
C7
D7
8
8
D0 ACK
A0
C0 ACK
9
9
9
PD75518(A)
BUSY
BUSY
ACK
BUSY
READY
READY
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