UPD75518 NEC, UPD75518 Datasheet - Page 102

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

SB0/SB1
IRQCSI0
102
(3) Two-wire serial I/O mode
SCK0
The two-wire serial I/O mode can be made compatible with any communication format by programming.
In this mode, communication is basically performed using two lines: Serial clock (SCK0) and serial data
input/output (SB0 or SB1).
(a) Communication operation
The two-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by
bit in phase with the serial clock.
The shift register 0 performs shift operation on the falling edge of the serial clock (SCK0). Transmit
data is latched on the SO0 latch, and is output on the SB0/P02 pin or SB1/P03 pin starting with the
MSB. Receive data applied to the SB0 pin or SB1 pin is latched in the shift register on the rising edge
of SCK0.
When eight bits have been transferred, shift register 0 operation automatically terminates setting the
interrupt request flag (IRQCSI0).
The SB0 or SB1 pin becomes an N-ch open-drain I/O when specified as the serial data bus, so the
voltage level on that pin must be pulled up externally.
The state of the SO0 latch is output on the SB0 or SB1 pin, so the SB0 or SB1 pin output states can
be controlled by setting the RELT or CMDT bit.
However, this operation must not be performed during serial transfer.
The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the output
mode (internal system clock mode). (See Section 4.8.7.)
Fig. 4-46 Timing of Two-Wire Serial I/O Mode
1
D7
2
Transfer is started in phase with falling edge of SCK0.
Execution of instruction that writes date to SIO0 (Transfer start request)
D6
3
D5
4
D4
5
D3
6
D2
7
D1
Completion of transfer
PD75518(A)
8
D0