UPD75518 NEC, UPD75518 Datasheet - Page 120

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

120
(4) SA register (successive approximation register)
(5) A/D converter operation
Setting values of SCC, PCC
SCC1
The SA register is an 8-bit register to hold the result of A/D conversion in successive approximation.
SA is read with an 8-bit manipulation instruction. No data can be written to SA by software.
The generation of a RESET signal makes SA undefined.
SA is mapped to address FDAH.
Analog input signals subject to A/D conversion are specified by setting bits 6, 5, and 4 in the A/D conversion
mode register (ADM6, ADM5, and ADM4). Comparator bias voltage selection is specified by setting bit
1 in the A/D conversion mode register (ADM1).
A/D conversion is started by setting bit 3 (SOC) of ADM to 1. After that, SOC is automatically cleared to
0. A/D conversion is performed by hardware using the successive-approximation method. The resultant
8-bit data is loaded into the SA register. Upon completion of A/D conversion, ADM bit 2 (EOC) is set to 1.
Fig. 4-59 shows the timing chart of A/D conversion.
The A/D converter is used as follows:
1
2
3
4
Cautions 1. 1 and 2 above can be performed at the same time.
0
0
1
Note 40.1 s for f
Remark
Select analog input channels and comparator bias voltage (by setting ADM6, ADM5, ADM4, and
ADM1).
Direct the start of A/D conversion (by setting SOC).
Wait for the completion of A/D conversion (wait for EOC to be set or wait using a software timer).
Read the result of A/D conversion (read the SA register).
SCC0
0
1
2. There is a delay of up to 2
: Don’t care
PCC1
the setting of SOC to the clearing of EOC after A/D conversion is started. EOC must be tested
when a time indicated in Table 4-11 has elapsed after the setting of SOC. Table 4-11 also
indicates A/D conversion times.
0
0
1
1
PCC0
X
0
1
0
1
= 4.19 MHz
168/f
(28.0 s/f
Conversion stopped
A/D conversion time
X
s
Table 4-11 Setting of SCC and PCC
Note
X
= 6.0 MHz)
4
/f
X
seconds (f
Waiting not required
1 machine cycle
2 machine cycles
4 machine cycles
Waiting not required
Wait time from SOC setting
to EOC test
X
= 6.0 MHz: 2.67 s, or f
—
X
Wait time from SOC setting
to A/D conversion comple-
tion
3 machine cycles
11 machine cycles
21 machine cycles
42 machine cycles
Waiting not required
= 4.19 MHz: 3.81 s) from
—
PD75518(A)