wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 11

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

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Production Data
Test Conditions
DCVDD = 1.8V, DBVDD = 3.3V, AVDD = 3.3V, T
PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
Analogue Reference Levels
VMID Midrail Reference Voltage
Microphone Bias
Bias Voltage
Bias Current Source
Output Noise Density
AVDD PSRR (217Hz)
Digital Input / Output
Input HIGH Level
Input LOW Level
Note that digital input pins should not be left unconnected / floating.
Internal pull-up/pull-down resistors may be enabled on GPIO3, GPIO4 and GPIO5 if required.
Output HIGH Level
Output LOW Level
Input capacitance
Input leakage
PLL
Input Frequency
Lock time
GPIO
Clock output duty cycle
(Integer OPCLKDIV)
Clock output duty cycle
(Non-integer OPCLKDIV)
Interrupt response time for accessory /
button detect
A
100mV pk-pk @217Hz
SYSCLK=PLL output;
SYSCLK=PLL output;
SYSCLK=PLL output;
Input not de-bounced
TEST CONDITIONS
= +25
OPCLKDIV=0000
OPCLKDIV=1000
OPCLKDIV=0000
OPCLKDIV=1000
OPCLKDIV=0100
OPCLKDIV=0100
Input de-bounced
Input de-bounced
3mA load current
3mA load current
PRESCALE = 0b
PRESCALE = 1b
SYSCLK=MCLK;
SYSCLK=MCLK;
SYSCLK=MCLK;
1kHz to 20kHz
TOCLKSEL=1
MBSEL=0
MBSEL=1
I
on AVDD
I
OH
OL
o
C, 1kHz signal, fs = 48kHz,
=-1mA
=1mA
0.7×DBVDD
0.9×DBVDD
2
2
21
19
14.4
/ f
/ f
-3%
-5%
-5%
-0.9
MIN
7.7
35
45
45
45
33
33
SYSCLK
SYSCLK
0.65×AVDD
0.9×AVDD
AVDD/2
TYP
100
200
45
10
0
PD, January 2009, Rev 4.0
0.3×DBVDD
0.1×DBVDD
2
2
22
20
+3%
+5%
+5%
MAX
/ f
/ f
0.9
18
36
65
55
55
55
66
66
3
SYSCLK
SYSCLK
WM8953
nV/√Hz
UNIT
MHz
MHz
mA
dB
pF
uA
us
%
%
%
%
%
%
V
V
V
V
V
V
V
s
s
s
11