wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 36

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

WM8953
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ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8953 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback
and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC full
scale input level is proportional to AVDD. See “Electrical Characteristics” for further details. Any input
signal greater than full scale may overload the ADC and cause distortion.
The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits. If both ADCs are to be
enabled, they should be enabled simultaneously, i.e. with the same register write. If there is a
requirement to enable the ADCs independently of one another and use them simultaneously, the
ADCL_ADCR_LINK bit should be set. The EXT_ACCESS_ENA bit must be set before writing to the
ADCL_ADCR_LINK bit.
Table 12 ADC Enable Control
ADC DIGITAL VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to
+17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for
a given eight-bit code X is given by:
0.375 × (X-192) dB for 1 ≤ X ≤ 239;
The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the
ADCL_VOL or ADCR_VOL control data will be loaded into the respective control register, but will not
actually change the digital gain setting. Both left and right gain settings are updated when a 1 is
written to ADC_VU. This makes it possible to update the gain of both channels simultaneously.
Table 13 ADC Digital Volume Control
R2 (02h)
R117 (75h)
R122 (7Ah)
R15 (0Fh)
R16 (10h)
REGISTER
REGISTER
ADDRESS
ADDRESS
1
0
1
15
8
7:0
8
7:0
BIT
BIT
ADCL_ENA
(rw)
ADCR_ENA
(rw)
EXT_ACCESS_ENA
ADCL_ADCR_LINK
ADC_VU
ADCL_VOL
[7:0]
ADC_VU
ADCR_VOL
[7:0]
LABEL
LABEL
MUTE for X = 0
N/A
1100_0000b
(0dB)
N/A
1100_0000b
(0dB)
DEFAULT
0b
0b
0b
0b
DEFAULT
+17.625dB for 239 ≤ X ≤ 255
ADC Volume Update
Writing a 1 to this bit will cause left
and right ADC volume to be updated
simultaneously
Left ADC Digital Volume
(See Table 14 for volume range)
ADC Volume Update
Writing a 1 to this bit will cause left
and right ADC volume to be updated
simultaneously
Right ADC Digital Volume
(See Table 14 for volume range)
0 = ADC disabled
1 = ADC enabled
0 = ADC disabled
1 = ADC enabled
Extended Register Map Access
0 = disabled
1 = enabled
0 = ADC Sync disabled
1 = ADC Sync enabled
Left ADC Enable
Right ADC Enable
DESCRIPTION
PD, January 2009, Rev 4.0
DESCRIPTION
Production Data
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