wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 22

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wm8953

Manufacturer Part Number
wm8953
Description
Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
Manufacturer
Wolfson Microelectronics plc
Datasheet
WM8953
w
CONTROL INTERFACE TIMING – 4-WIRE MODE
Figure 9 Control Interface Timing – 4-Wire Serial Control Mode (Write Cycle)
Figure 10 Control Interface Timing – 4-Wire Serial Control Mode (Read Cycle)
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=3.3V, DGND=AGND=0V, T
otherwise stated.
Program Register Input Information
SCLK rising edge to CSB falling edge
SCLK falling edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SDIN to SCLK hold time
SDOUT propagation delay from SCLK rising edge
Pulse width of spikes that will be suppressed
SCLK falling edge to SDOUT transition
SDOUT
SCLK
CSB
PARAMETER
4-wire mode supports readback via SDOUT which is available as a GPIO pin function.
t
DL
A
=+25
SYMBOL
t
t
t
t
t
t
t
CSU
CHO
SCH
DSU
DHO
t
t
SCY
SCL
t
o
DL
DL
ps
C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless
LSB
MIN
200
40
40
80
80
40
10
0
TYP
PD, January 2009, Rev 4.0
MAX
10
40
5
Production Data
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22

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