wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 23
wm8953
Manufacturer Part Number
wm8953
Description
Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8953.pdf
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Production Data
INTERNAL POWER ON RESET CIRCUIT
Figure 12 Typical Power up Sequence where AVDD is Powered before DCVDD
Figure 11 Internal Power on Reset Circuit Schematic
The WM8953 includes an internal Power-On-Reset Circuit, as shown in Figure 11, which is used to
reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and
monitors DCVDD. It asserts PORB low if AVDD or DCVDD is below a minimum threshold.
Figure 12 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above
the minimum threshold, V
low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now
AVDD is at full supply level. Next DCVDD rises to V
registers are in their default state and writes to the control interface may take place.
On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the
minimum threshold V
pora_off
pora
.
, there is enough voltage for the circuit to guarantee PORB is asserted
pord_on
and PORB is released high and all
PD, January 2009, Rev 4.0
WM8953
23
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