wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 84

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

WM8953
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REGISTER BITS BY ADDRESS
R0 (00h)
Reset / ID
R1 (01h)
Power
Management
(1)
R02 (02h)
Power
Management
(2)
REGISTER
ADDRESS
15:0
15:8
7:5
4
3
2:1
0
15
14
13:12
11
10
9
8
7
6
5
4
3:2
1
BIT
SW_RESET_CHIP_
ID
[15:0]
(rr)
MICBIAS_ENA
(rw)
VMID_MODE
[1:0]
(rw)
VREF_ENA
(rw)
PLL_ENA
(rw)
TSHUT_ENA
(rw)
OPCLK_ENA
(rw)
AINL_ENA
(rw)
AINR_ENA
(rw)
LIN34_ENA
(rw)
LIN12_ENA
(rw)
RIN34_ENA
(rw)
RIN12_ENA
(rw)
ADCL_ENA
(rw)
LABEL
8990h
00h
000b
0b
0b
00b
0b
0b
1b
10b
0b
0b
0b
0b
0b
0b
0b
0b
00b
0b
DEFAULT
Writing to this register resets all registers to their default state.
Reading from this register will indicate device family ID 8990h.
Reserved - Do Not Change
Reserved - Do Not Change
MICBIAS Enable
0 = OFF (high impedance output)
1 = ON
Reserved - Do Not Change
Vmid Divider Enable and Select
00 = Vmid disabled (for OFF mode)
01 = 2 x 50kΩ divider (Normal mode)
10 = 2 x 250kΩ divider (Standby mode)
11 = 2 x 5kΩ divider (for fast start-up)
VREF Enable (Bias for all analogue functions)
0 = VREF bias disabled
1 = VREF bias enabled
PLL Enable
0 = disabled
1 = enabled
Thermal Sensor Enable
0 = Thermal sensor disabled
1 = Thermal sensor enabled
Reserved - Do Not Change
GPIO Clock Output Enable
0 = disabled
1 = enabled
Reserved - Do Not Change
Left Input Path Enable
0 = disabled
1 = enabled
Right Input Path Enable
0 = disabled
1 = enabled
LIN34 Input PGA Enable
0 = disabled
1 = enabled
LIN12 Input PGA Enable
0 = disabled
1 = enabled
RIN34 Input PGA Enable
0 = disabled
1 = enabled
RIN12 Input PGA Enable
0 = disabled
1 = enabled
Reserved - Do Not Change
Left ADC Enable
0 = disabled
1 = enabled
DESCRIPTION
PD, January 2009, Rev 4.0
Production Data
84